1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing such a device. More particularly, the present invention relates to a semiconductor device having a pillar-shaped capacitor storage node having a high dielectric film and a method for manufacturing such a device.
2. Background of the Invention
Conventional dynamic random access memory (DRAM) devices include storage nodes, which storage nodes typically include a capacitor. As DRAM devices are scaled down to a line width dimension of about a quarter micrometer, two-dimensional areas occupied by the capacitor become smaller and smaller. Despite reduced cell areas, capacitors require a minimum level of capacitance of about 25 fF to 30 fF. Many methods have therefore been developed to maintain a desired capacitance from decreased two-dimensional areas.
One approach is to increase the height of the capacitor so as to increase the available cell surface areas. The increase in the height of the capacitor at the cell array region, however, causes a large step between the cell array region and peripheral region, thus making it difficult to form metal interconnections.
An alternative approach is to increase the dielectric constant of the dielectric film of the capacitor. Recently, high dielectric materials such as strontium titanate (SrTiO.sub.3), barium-strontium titanate ((Ba.cndot.St)TiO.sub.3), and the like, having a dielectric constant of more than 10,000, have been adopted as a dielectric film instead of the conventional silicon nitride (Si.sub.3 N.sub.4) and tantalum oxide (Ta.sub.2 O.sub.5). However, when the polysilicon is used as a capacitor storage node, a layer of low dielectric characteristics, such as SiO.sub.2 (silicon oxide layer) is formed at the interface between the polysilicon layer and the high dielectric film, thereby increasing the leakage current of the high dielectric film.
Accordingly, there is a need for a storage node that is compatible with high dielectric materials, but which does not degrade the high dielectric characteristics. Because platinum is unreactive with a high dielectric layer during deposition and post-deposition annealing of the high dielectric layer, platinum has been employed as a capacitor storage node when the dielectric film is comprised of a high dielectric material, such as strontium titanate and barium-strontium titanate. However, there are some problems associated with the use of platinum in highly integrated circuit devices. For example, when applied to a process for forming a storage node with about 0.1 to 0.2 micrometers spacing, etched platinum is left on the sidewalls of the patterned storage node. This may occur because it is difficult to form volatile etching by-products during dry etching of the platinum, and so etching by-products remain. As a result, the final storage node has a sloped sidewall profile, and such a sidewall profile can be a serious obstacle to achieving fine pattern size. Also, in severe cases, an electrical bridge may arise between adjacent storage nodes.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.